This invention relates to information storage and retrieval or transmission systems, and more particularly to means for encoding and decoding codewords for use in error detection and correction in such information systems.
Digital information storage devices, such as magnetic disk, magnetic tape or optical disk, store information in the form of binary bits. Also, information transmitted between two digital devices, such as computers, is transmitted in the form of binary bits. During transfer of data between devices, or during transfer between the storage media and the control portions of a device, errors are sometimes introduced so that the information received is a corrupted version of the information sent. Errors can also be introduced by defects in a magnetic or optical storage medium. These errors must almost always be corrected if the storage or transmission device is to be useful.
Correction of the received information is accomplished by (1) deriving additional bits, called redundancy, by processing the original information mathematically; (2) appending the redundancy to the original information during the storage or transmission process; and (3) processing the received information and redundancy mathematically to detect and correct erroneous bits at the time the information is retrieved. The process of deriving the redundancy is called encoding. One class of codes often used in the process of encoding is Reed-Solomon codes.
Encoding of information is accomplished by processing a sequence of information bits, called an information polynomial or information word, to devise a sequence of redundancy bits, called a redundancy polynomial, in accord with an encoding rule such as one of the Reed-Solomon codes. An encoder processes the information polynomial with the encoding rule to create the redundancy polynomial and then appends it to the information polynomial to form a codeword polynomial which is transmitted over the signal channel or stored in an information storage device. When a received codeword polynomial is received from the signal channel or read from the storage device, a decoder processes the received codeword polynomial to detect the presence of error(s) and to attempt to correct any error(s) present before transferring the corrected information polynomial for further processing.
Symbol-serial encoders for Reed-Solomon error correcting codes are known in the prior art (see Riggle, U.S. Pat. No. 4,413,339). These encoders utilize the conventional or standard finite-field basis but are not easy to adapt to bit-serial operation. Bit-serial encoders for Reed-Solomon codes are also known in the prior art (see Berlekamp, U.S. Pat. No. 4,410,989 and Glover, U.S. Pat. No. 4,777,635). The Berlekamp bit-serial encoder is based on the dual basis representation of the finite field while the bit-serial encoder of U.S. Pat. No. 4,777,635 is based on the conventional representation of the finite field. Neither U.S. Pat. No. 4,410,989 nor U.S. Pat. No. 4,777,635 teach methods for decoding Reed-Solomon codes using bit-serial techniques.
It is typical in the prior art to design encoding and error identification apparatus where n=m=8 bits, where n is the number of bits in a byte and m is the symbol size (in bits) of the Reed-Solomon code. However, this imposes a severe restriction on the information word length: since the total of information bytes plus redundancy symbols must be less than 2.sup.m, no more than 247 information bytes may appear in a single information word if 8 redundancy symbols are to be used. Increasing media densities and decreasing memory costs push for increasing the size of information words. Thus, there is a need to decouple n, the byte-size of the information word, from m, the symbol size of the Reed-Solomon code employed.
Also, bit-serial finite-field constant multiplier circuits are well known in the prior art. For example, see Glover and Dudley, Practical Error Correction Design for Engineers (Second Edition), pages 112-113, published by Data Systems Technology Corp., Broomfield, Colo. However, these designs require that the most-significant (higher order) bit of the code symbol be presented first in the serial input stream. Using exclusively multipliers with this limitation to implement an error identification circuit results in the bits included in a burst error not being adjacent in the received word symbols. Thus, there is a need for a least-significant-bit first, bit-serial, finite-field constant multiplier.
Prior-art circuits used table look-up to implement the finite-field arithmetic operation of multiplication, which is used in the error-identification computation. Because the look-up table size is established by 2.sup.m, the number of bits in each code symbol, even a modest increase in m results in a substantial increase in the look-up table size. It is possible to reduce the size of the required tables, at the expense of the multiplication computation time, by representing the finite field elements as the concatenation of two elements of a finite field whose size is significantly less than the size of the original field. However, there are situations in which one would like to be able to choose implementations at either of two points on the speed-versus-space tradeoff to accomplish either fast correction using large tables or slower correction using small tables. Thus, there is a need for a way of supporting either implementation of finite-field arithmetic in error correcting computations.
As the recording densities of storage devices increase, the rate of occurrence for soft errors (non-repeating noise related errors) and hard errors (permanent defects) increase. Soft errors adversely affect performance while hard errors affect data integrity.
Errors frequently occur in bursts e.g. due to a noise event of sufficient duration or a media defect of sufficient size to affect more than one bit. It is desirable to reduce the impact of single-burst errors by correcting them on-the-fly, without re-reading or re-transmitting, in order to decrease data access time. Multiple, independent soft or hard errors affecting a single codeword occur with frequency low enough that performance is not seriously degraded when re-reading or off-line correction is used. Thus, there is a need for the capability to correct a single-burst error in real time and a multiple-burst error in an off-line mode.
Due to market pressure there is a continuous push toward lower manufacturing cost for storage devices. This constrains the ratio of the length of the redundancy polynomial to the length of the information polynomial.
It is thus apparent that there is a need in the art for higher performance, low cost implementations of more powerful Reed-Solomon codes.
FIG. 1A shows the prior art classical example of a Reed-Solomon linear feedback shift register (LSFR) encoder circuit that implements the code generator polynomial EQU x.sup.4 +c.sub.3 x.sup.3 +c.sub.2 x.sup.2 +c.sub.1 x+c.sub.0
over the finite field GF(2.sup.m). The elements 121, 122, 123, and 124 of the circuit are m-bit wide, one-bit long registers. Data bits grouped into symbols being received on data path 125 are elements of the finite field GF(2.sup.m). Prior to transmitting or receiving, register stages 121, 122, 123, 124 are initialized to some appropriate starting value; symbol-wide logic gate 128 is enabled; and multiplexer 136 is set to connect data path 125 to data/redundancy path 137. On transmit, data symbols from data path 125 are modulo-two summed by symbol-wide EXCLUSIVE-OR gate 126 with the high order register stage 121 to produce a feedback symbol on data path 127. The feedback symbol on data path 127 then passes through symbol-wide logic gate 128 and is applied to finite field constant multipliers 129, 130, 131, and 132. These constant multipliers multiply the feedback symbol by each of the coefficients of the code generator polynomial. The outputs of the multipliers 129, 130, and 131, are applied to symbol-wide summing circuits 133, 134, and 135 between registers 121, 122, 123, and 124. The output of multiplier 132 is applied to the low order register 124.
When the circuit is clocked, register 121, 122, and 123 take the values at the outputs of the modulo-two summing circuits 133, 134, and 135, respectively. Register 124 takes the value at the output of constant multiplier 132. The operation described above for the first data symbol continues for each data symbol through the last data symbol. After the last data symbol is clocked, the REDUNDANCY TIME signal 138 is asserted, symbol-wide logic gate 128 is disabled, and symbol-wide multiplexer 136 is set to connect the output of the high order register 121 to the data/redundancy path 137. The circuit receives 4 additional clocks to shift the check bytes to the data/redundancy path 137. The result of the operation described above is to divide an information polynomial I(x) by the code generator polynomial G(x) to generate a redundancy polynomial R(x) and to append the redundancy polynomial to the information polynomial to obtain a codeword polynomial C(x). Circuit operation can be described mathematically as follows: EQU R(x)=(x.sup.4 *I(x))MOD G(x) EQU C(x)=x.sup.4 *I(x)+R(x)
where + means modulo-two sum and * means finite field multiplication.
FIG. 1B shows a prior art example of an external-XOR Reed-Solomon LFSR encoder circuit that implements the same code generator polynomial as is implemented in FIG. 1A, though FIG. 1A uses the internal-XOR form of LFSR. Internal-XOR LFSR circuits always have an XOR (or parity tree or summing) circuit between shift register stages containing different powers of X, whereas external-XOR circuits do not have a summing circuit between all such shift register stages. In addition, internal-XOR LFSR circuits always shift data toward the stage holding the highest power of X, whereas external-XOR circuits always shift data toward the stage holding the lowest power of X. External-XOR LFSR circuits are known to the prior art (for example, see Glover and Dudley, Practical Error Correction for Engineers pages 32-34, 181, 296 and 298).
FIG. 2 is a block diagram of another prior art encoder and time domain syndrome generation circuit which operates on m-bit symbols from GF(2.sup.m), k bits per clock cycle where k evenly divides m. The circuit of FIG. 2 employs the conventional finite field representation and performs the same function as the encoder shown in FIG. 1 except that it is easily adapted to operate on k bits of an m-bit symbol per clock, where k evenly divides m.
The circuit of FIG. 2 utilizes n registers, here represented by 160, 161, 162, and 163, where n is the degree of the code generator polynomial. The input and output paths of each register are k bits wide. The depth (number of delay elements between input and output) of each register is m/k. When k is less than m, each of the registers 160, 161, 162, and 163 function as k independent shift registers, each m/k bits long. Prior to transmitting or receiving, all registers 160, 161, 162, and 163 are initialized to some appropriate starting value; logic gates 164 and 165 are enabled; and multiplexer 166 is set to pass data from logic gate(s) 165 to data/redundancy path 167. On transmit, data symbols from data path 168 are modulo-two summed by EXCLUSIVE-OR gate(s) 169 with the output of the high order register 160, k bits at a time, to produce a feedback signal at 170. The feedback signal is passed through gate(s) 164 to the linear network 171 and to the next to highest order register 161. The output of register 161 is fed to the next lower order register 162 and so on. The output of all registers other than the highest order register 160 also have outputs that go directly to the linear network 171. Once per m-bit data symbol the output of linear network 171 is transferred, in parallel, to the high order register 160.
When k is equal to m, the linear network 171 is comprised only of EXCLUSIVE-OR gates. When k is not equal to m, the linear network 171 also includes linear sequential logic components. On each clock cycle, each register is shifted to the right one position and the leftmost positions of each register take the values at their inputs. The highest order register 160 receives a new parallel-loaded value from the linear network 171 once per m-bit data symbol. Operation continues as described until the last data symbol on data path 168 has been completely clocked into the circuit. Then the REDUNDANCY TIME signal 175 is asserted, which disables gates 164 and 165 (because of INVERTER circuit 178) and changes multiplexer 166 to pass the check symbols (k bits per clock) from the output of the modulo-two summing circuit 169 to the data/redundancy path 167. Clocking of the circuit continues until all redundancy symbols have been transferred to the data/redundancy path 167. The result of the operation described above is that the information polynomial I(x) is divided by the code generator polynomial G(x) to generate a redundancy polynomial R(x) which is appended to the information polynomial I(x) to obtain the codeword polynomial C(x). This operation can be described mathematically as follows: EQU R(x)=(x.sup.m *I(x))MOD G(x) EQU C(x)=x.sup.m *I(x).sym.R(x)
In receive mode, the circuit of FIG. 2 operates as for a transmit operation except that after all data symbols have been clocked into the circuit, RECEIVE MODE signal 176, through OR gate 177, keeps gate(s) 165 enabled while REDUNDANCY TIME signal 175 disables gate(s) 164 and changes multiplexer 166 to pass time domain syndromes from the output of modulo-two summing circuit 169 to the data-redundancy path 167. The circuit can be viewed as generating transmit redundancy (check bits) during transmit, and receive redundancy during receive. Then the time domain syndromes can be viewed as the modulo-two difference between transmit redundancy and receive redundancy. The time domain syndromes are decoded to obtain error locations and values which are used to correct data. Random access memory (RAM) could be used as a substitute for registers 160, 161, 162, and 163.